module scancode_ram(flag, flag1, clk, addr,outdata);
input flag; // shift
input flag1;
input clk;
input [7:0] addr;
output reg [7:0] outdata;
reg [7:0] ascii_tab[255:0];
initial begin
	$readmemh("D:/Seafile/Seafile/FPGA/DE10/Tool/SystemBuilder/CodeGenerated/DE10_Standard/exp07pro/scancode.mif", ascii_tab, 0, 255);
end
wire [7:0]ascii;
assign ascii = ascii_tab[addr];
always@(*)begin
	if(flag)begin
		if("a" <= ascii && ascii <= "z") begin
			outdata <= ascii - 8'h20;
		end else begin
			case(ascii)
				";":begin
					outdata <= ":";
				end
				"'":begin
					outdata <= "\"";
				end
				",":begin
					outdata <= "<";
				end
				".":begin
					outdata <= ">";
				end
				"/":begin
					outdata <= "?";
				end
				"[":begin
					outdata<="{";
				end
				"]":begin
					outdata <= "}";
				end
				"-":begin
					outdata <= "_";
				end
				"=":begin
					outdata <= "+";
				end
				8'h5c:begin
					outdata <= "|";
				end
				"`":begin
					outdata <= "~";
				end
				"1" : begin
					outdata <= "!";
				end
				"2" : begin
					outdata <= "@";
				end
				"3" :begin
					outdata <= "#";
				end
				"4":begin
					outdata <= "$";
				end
				"5":begin
					outdata <= "%";
				end
				"6":begin
					outdata <= "^";
				end
				"7":begin
					outdata <= "&";
				end
				"8":begin
					outdata <= "*";
				end
				"9":begin
					outdata <= "(";
				end
				"0":begin
					outdata <= ")";
				end
				default :begin
					outdata <= ascii;
				end
			endcase
		end
	end else begin
		outdata = ascii;
	end
end
//assign outdata = ((flag || flag1) && addr!=8'h00)?(ascii_tab[addr]-8'h20):ascii_tab[addr];
endmodule